Dsg d  n q   &f&i page &p of &nArialdo z @ E?"@y +Z#H@8@F?8@F@8@F?8@F@8hidg@ {\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\qj \x\fs16\b LOAD INPUTS\par \qj \x\fs16 These are inputs to allow the counter to be set to any value when LD=1} }"F ppppp"F0FW0ppppp"Fp~P0ppppp"Fppppp"Eb{F    `{"Z#"Eb{ކgF''g`{g"Z# "Eb{^/F`@_`@_/`{/"Z#"Eb{NKFN CN CK`{K"Z# "Fг1  "Eb{>BF@`{@"Z# "Fp@PQ0ppppp"Eb{^HFH H ``{`"Z#dg  {\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\ql \x\fs16\b DIRECTION\par \ql \x\fs16 0=Down, 1=Up} }"F00ppppp"Eb{~`{''FZ#"dg`  {\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\qj \x\fs16\b RESET\par \qj \x\fs16 Outputs reset to 0000 while RESET input =1} }"FТ0ppppp"Eb{b`{ C C`F`Z#"dg`)'{\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\qj \x\fs16\b LOAD\par \qj \x\fs16 Outputs = L1,L2,L4,L8 when LD=1. This allows the counter to s\x\fs16 tart from any value.} }d b {\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\qj \x\fs16\b\ul Priority of Controls\par \qj \x\fs16 Some controls overide others. Below is a list of controls in \x\fs16 heirachical order. The ones at the top take priority over the\x\fs16 ones following.\par \qj \x\fs16 \par \qj \x\fs16 RESET - over-rides all other inputs - sets output = 0000\par \qj \x\fs16 LOAD - over-rides counting and enable\par \qj \x\fs16 ENABLE - over-rides clock input\par \qj \x\fs16 CLOCK - lowest priority.} }"F:K0pppppdg`'{\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\qj \x\fs16\b ENABLE/CARRYIN\par \qj \x\fs16 When =1, the counter is frozen. Also acts a carry in from pre\x\fs16 vious stage.} }" Pp$ I I I I I"$^/ $/@@/@@``Z#"" @\ I I I I I" $NKN`\N`\K $K"Z# " x I I I I I" 0 I I I I I" $ކgxxg $g"Z# " $ $  Z#"" Eb{,"C`{,@_,@_ CF CZ#"" : I I I I I" $,,, $,"Z#dY ``{\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\ql \x\fs16\b CARRYOUT\par \qj \x\fs16 Goes low prior to a carry. For example, when o/p=15 counting \x\fs16 up and when o/p=0 counting down\x\fs20 .} }dYr @ {\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\qj \x\fs16\b BINARY OUTPUTS\par \qj \x\fs16 These are the binary outputs which count between 0 to 15.} }d9:W{\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\qj \x\fs16 1} }d 9:sW{\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\qj \x\fs16 2} }d 9s^W{\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\qj \x\fs16 4} }d 9^W{\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\qj \x\fs16 8} }d g``{\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\ql \x\fs16\b CLOCK\par \ql \x\fs16 Input for clock pulses} }d gr {\rtf1\ansi\deff0\deftab254{\fonttbl{\f0\fnil\fcharset0 Arial;}}{\pard\qc \x\fs28\b CMOS 4516 IC\par \qc \x\fs24\b 4-bit UP/DOWN SYNCHRONOUS PRESETTABLE BINARY COUNTER} }@ @?"@